Tesla Terafab Semiconductor Supply Chain

Tesla Terafab — announced March 21, 2026, at the Seaholm Power Plant site in Austin, Texas — is the most significant vertical integration event in the semiconductor industry since TSMC's founding in 1987. A joint venture between Tesla, SpaceX, and xAI, Terafab is the third tier in a deliberate three-tier fab strategy that Tesla has assembled over the preceding two years. Understanding Terafab requires understanding the full three-tier architecture: a captive-equivalent dedicated line at Samsung Taylor Texas for AI5, a shared external foundry relationship at TSMC Arizona for AI5 supply resilience, and Terafab itself as the owned production base for AI6 and AI7. Each tier serves a different chip family, operates under a different ownership and control model, and addresses a different supply chain risk.

This page covers the supply chain and semiconductor architecture of all three tiers: the Samsung Taylor captive arrangement, the AI5 dual-fab strategy, AI6 for Cybercab and Optimus, AI7 for SpaceX orbital compute, and what Terafab's stated targets imply for the global semiconductor supply chain. For the deployment layer — what these chips mean for Tesla vehicles, Optimus robots, Cybercab robotaxis, and energy infrastructure — see ElectronsX: Tesla Terafab & Silicon Strategy.

The Three-Tier Fab Strategy

Tesla's semiconductor manufacturing architecture is not a single bet on Terafab. It is a layered strategy that provides supply chain resilience at each stage of the chip family roadmap while Terafab is being built. The three tiers differ in ownership, control model, chip family served, and risk profile — and each tier was assembled to address the specific supply chain risk of the tier above it.

Samsung Taylor — Captive Without Ownership

The Samsung Taylor arrangement is the most operationally significant and least-discussed element of Tesla's semiconductor strategy. Under a 10-year exclusive supply agreement, Samsung's Taylor Texas fab is 100% dedicated to Tesla AI5 production — not shared with other Samsung foundry customers. Tesla engineers have on-premise access to the production line, with the right to observe operations, participate in yield improvement programs, and propose process optimizations. This is not a standard foundry customer relationship. It functions in practice as a captive fab that appears on Samsung's balance sheet rather than Tesla's.

The on-premise engineering access is the most commercially unusual element of the arrangement. Standard foundry agreements maintain strict separation between fab operations and customer engineers — customers receive processed wafers and yield data, not access to the production floor. Tesla's on-prem access is only extractable from a foundry when the customer is the sole occupant of a dedicated line: Samsung cannot protect process secrets from a customer who is already the only customer seeing the full process. When Tesla engineers identify a tool setting, recipe parameter, or maintenance practice that improves AI5 yield, Samsung has every incentive to implement it — the improvement benefits both parties and Samsung loses nothing by sharing it with a customer who sees the full line. This creates a continuous process improvement loop — walking the line and offering improvements to productivity and optimization — that no shared-foundry customer participates in. It is the operational equivalent of owning a fab without carrying the capital on Tesla's balance sheet.

AI5 — High-Performance Inference at External Dual-Fab

AI5 is Tesla's fifth-generation inference SoC — the successor to HW4 currently deployed in production vehicles. It is a high-performance, high-power device produced entirely at external foundries: Samsung Taylor (100% dedicated line) and TSMC Arizona (shared allocation). AI5 is not a Terafab product. It is the bridge chip that powers Tesla's vehicle fleet, datacenter inference, and Dojo successor training infrastructure while Terafab is built and AI6/AI7 are developed. The dual-fab strategy eliminates the single-point-of-failure risk that cost the automotive industry billions during the 2021-2022 chip shortage — a disruption at either fab does not stop AI5 production entirely.

AI6 — Low-Power SoC for Cybercab and Optimus

AI6 is the Terafab primary product for ground-based deployment — a low-power inference SoC designed for the size, weight, and power constraints of the Cybercab robotaxi and Optimus humanoid robot. Where AI5 accepts high TDP in exchange for maximum TOPS, AI6 inverts the tradeoff: maximum inference efficiency per watt within a thermal budget compatible with compact robotaxi architecture and humanoid robot battery capacity. A Cybercab running AI5 at 700-800W would require a thermal management system that consumes significant vehicle volume, weight, and battery capacity — degrading range and increasing BOM cost in ways that undermine robotaxi unit economics. AI6 at a fraction of AI5's TDP achieves the same FSD inference capability because it is co-designed with Tesla's model architecture, not adapted from a general-purpose compute device.

AI6 is a Terafab chip for two compounding reasons. First, volume: at 100 million Optimus units annually — Tesla's stated target — AI6 production requires wafer volumes that cannot be sourced from shared external foundry capacity without displacing other customers and accepting allocation uncertainty that Tesla's production schedule cannot tolerate. Second, co-design advantage: AI6 will be co-designed with Terafab's 2nm process from first principles, enabling optimizations in transistor architecture, memory subsystem, and power delivery that external foundry PDKs cannot accommodate for a single customer. The chip and the fab will evolve together in a closed loop that external foundry customers cannot replicate regardless of negotiating leverage.

AI7 — Low-Power Rad-Tolerant SoC for SpaceX Orbital Compute

AI7, also referred to as D3, is the SpaceX-specific chip in the Terafab product family — a low-power, radiation-tolerant inference SoC designed for continuous AI compute in low Earth orbit across the Starlink constellation and successor satellite platforms. The radiation-tolerant specification — rather than radiation-hardened — reflects the LEO deployment environment and the distinction matters for process design.

Full radiation-hardening (designed to survive nuclear weapon EMP per MIL-STD-461) requires silicon-on-insulator substrates, enclosed layout transistors across the full chip, and hermetically sealed ceramic packaging. This level of protection is appropriate for military command-and-control systems and deep space probes, not commercial LEO constellations. Radiation-tolerant design for LEO addresses the actual threat environment: accumulated total ionizing dose over 5-10 year mission lifetime, single-event upsets from proton and heavy ion events at LEO altitudes, and thermal cycling from orbital day-night transitions. The mitigation set is a subset of full rad-hardening — hardened cell libraries for critical flip-flops and SRAM, error-correcting code on all memory, triple modular redundancy on safety-critical control paths, deep n-well guard rings for latch-up protection, and TID-tolerant process parameters — applied selectively to achieve mission-adequate reliability at substantially lower area and power penalty than full rad-hardening would impose on an AI inference SoC.

No commercial foundry will develop these process modifications and hardened cell libraries for a single customer at commercial satellite volumes. The AI7 process requirements are not exotic by military standards, but they are incompatible with sharing a standard commercial PDK line with other customers. Terafab's dedicated process environment, with Tesla and SpaceX engineers controlling the full process parameter space, is the only viable production path for AI7 at Starlink generation scales. The Starlink constellation growing from thousands to tens of thousands of satellites across future generations creates a sustained high-volume demand signal for AI7 that justifies a dedicated Terafab process line — and likely a process line that shares a base 2nm architecture with AI6 but applies radiation-tolerant design rule overlays and hardened cell library substitution as a co-existing variant rather than a fully separate process.

Terafab Structure — Scope and Scale

Equipment Requirements — The ASML Queue Problem

A 100,000 wspm 2nm fab requires approximately 15-20 EUV scanner systems — potentially including High-NA EUV (ASML EXE:5000 at $350M+ each) for the most critical GAA patterning layers. At ASML's production rate of 40-55 EUV systems per year globally, procuring 15-20 systems for Terafab requires a queue position reserved 2-3 years in advance of the target installation date. If Terafab targets first EUV tool installation in 2027-2028, the order must already be placed or in final negotiation. ASML does not sell EUV to new-entrant customers without a technical readiness review, site qualification, and relationship development period — a process that TSMC, Samsung, and Intel each went through over multiple years before receiving their first EUV systems. Terafab's EUV procurement is itself a multi-year supply chain challenge. See: Wafer Fab Equipment | Bottleneck Atlas

What the Three-Tier Strategy Proves

Tesla's three-tier fab architecture is the most sophisticated semiconductor supply chain strategy assembled by any automotive or robotics OEM. The Samsung Taylor captive arrangement required a 10-year volume commitment and a negotiating position only achievable by a customer willing to take 100% of a fab's output. The TSMC Arizona relationship required early adoption of Arizona fab production before TSMC had demonstrated N4/N2 volume yield at that site. Terafab requires $20-25B in capital, 5-7 years of buildout, and process engineering capability that currently exists only at TSMC, Samsung, and Intel. The barriers to competitive imitation are real and high on every dimension.

What the three-tier strategy does not resolve is the process development execution risk at Terafab itself. The Samsung Taylor captive arrangement and the TSMC Arizona relationship provide AI5 supply chain resilience through at least 2030. Terafab's AI6 and AI7 production depends on developing a 2nm process from first principles as a new-entrant fab operator — and Intel's decade-long struggle to close its process gap with TSMC is the cautionary precedent that the semiconductor industry applies to every new entrant at leading-edge nodes. Tesla's advantages over Intel in this comparison are genuine: a captive customer base that eliminates the commercial foundry customer acquisition problem, narrower chip design targets (AI6 and AI7 are purpose-built, not general-purpose), and a co-design approach that optimizes chip architecture and fab process simultaneously from day one. Whether those advantages are sufficient to achieve volume yield at 2nm on the timeline the roadmap implies is the open question the semiconductor industry will be watching for the next decade.

Related Coverage

SX Fab & Assembly: Fab & Assembly Overview | Fab List | Wafer Fab Equipment | Process Nodes & Lines | Advanced Packaging | CoWoS

SX Materials & IP: Semiconductor Bottleneck Atlas | EDA | U.S. Reshoring | CHIPS Act of 2022

SX Chip Types: AI Inference & Edge Compute SoCs | AI Accelerators | Memory & Storage | HBM

SX Sectors: Automotive & Mobility | Robotics & IoT | AI & ML | Space / Defense

SX Spotlights: Tesla EV Spotlight | Humanoid Robot Spotlight | Starlink Spotlight | NVIDIA Spotlight

EX Demand-Side (cross-network): EX: Tesla Terafab & Silicon Strategy | EX: Tesla EV Spotlight | EX: Humanoid Robots | EX: SDV Systems Supply Chain

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