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China Semiconductor Bifurcation
The China semiconductor bifurcation is the most consequential structural change in the global semiconductor supply chain since the foundry model emerged in the 1980s. For forty years, semiconductor supply chains were globally integrated by economic logic: design wherever the talent is, manufacture wherever the equipment and expertise are best (Taiwan, South Korea, Japan), package wherever labor is cheapest, and sell everywhere. Export controls, starting with the 2019-2020 Huawei Entity List actions and accelerating through the October 2022 BIS rules and their subsequent tightening, have broken this logic. The bifurcation is not a policy outcome that may or may not materialize — it has already materialized. Two parallel semiconductor supply chains now exist: one centered on TSMC, ASML, Applied Materials, Lam Research, KLA, SK Hynix, Micron, and Samsung serving the US-allied technology ecosystem; and one being built by SMIC, Hua Hong, CXMT, YMTC, NAURA, AMEC, and Huawei/HiSilicon serving the Chinese domestic technology ecosystem. These two supply chains are not equal in capability — the Western-aligned chain leads by approximately one decade in process technology — but they are increasingly separate, and the degree of technical separation grows with each successive round of export control tightening.
The SX framework for the bifurcation tracks it across six layers of the semiconductor supply chain: foundry (logic chip manufacturing), memory (DRAM and NAND), equipment (lithography, etch, deposition, metrology), materials (chemicals, gases, wafers), EDA/IP (design tools and standard cell libraries), and AI compute (accelerators and the software ecosystems that run on them). Bifurcation is most advanced in AI compute (Huawei Ascend ecosystem is functionally separate from NVIDIA/AMD), partially advanced in foundry and memory, and least advanced in equipment (SMIC and CXMT remain dependent on Western tools purchased before controls tightened). The key analytical question for each layer is not "is China capable of self-sufficiency?" but rather "what is the pace of domestic capability development relative to Western technology advancement, and does the gap narrow or widen over time?"
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Bifurcation Status by Supply Chain Layer
| Supply chain layer | China domestic capability (2026) | Western capability (2026) | Gap assessment | Bifurcation trajectory |
|---|---|---|---|---|
| Foundry — advanced logic | SMIC N+2 (7nm-class, DUV-only multipatterning): in volume production. SMIC N+3 (6nm-class): in development. Hua Hong: 90-28nm mature nodes. No EUV access = no sub-7nm density at commercial yield. SMIC 5nm in development with Huawei SciCarrier equipment support — not in production. | TSMC N2 (2nm-class GAA EUV): in volume production. Samsung SF2 (2nm GAA): in production. Intel 18A (GAA + PowerVia): in HVM. TSMC A16 (2026): in development. Gap = 5+ process generations. | ~10 year process node gap (SMIC at 2015-era TSMC equivalent density); DUV multipatterning ceiling at approximately 7nm-equivalent density; EUV ban is the mechanism maintaining this gap; gap structural for duration of EUV export control | Widening structurally — TSMC advances 1 node/year approximately while SMIC advances ~0.5 nodes/year; gap grows approximately 0.5 nodes/year under current export control regime; China compensates with density-for-density substitution (more dies per system) rather than chip-level performance parity |
| Foundry — mature nodes | SMIC, Hua Hong, CXMT, YMTC: strong 28nm-180nm capability. SMIC doubling advanced node capacity at Shanghai, Shenzhen, Beijing. ~50K WSPM 7nm-class capacity by end 2025. Very strong 28nm manufacturing — this is geopolitically the most contested frontier. | TSMC 28nm at multiple fabs; GlobalFoundries 12LP+; Samsung; Intel. Western 28nm capacity is not strategic concern — enough global capacity exists. US concern: SMIC 28nm becoming cost-competitive threatens Western mature node fabs (GlobalFoundries, TSMC mature nodes). | Minimal at 28nm and above; China is competitive or nearly so at mature nodes; 28nm is the stated US export control frontier for additional restrictions; SMIC expanding 28nm aggressively | Stable — 28nm bifurcation is largely complete; China is self-sufficient here. Policy question: do US controls extend to restrict 28nm tool exports (advanced DUV, etch, deposition) which would affect SMIC's expansion capacity |
| DRAM memory | CXMT (ChangXin Memory, Hefei): shipping DDR5 (2 years behind SK Hynix); DDR5 production at 257K WSPM capacity by 2026, ~15% of global DRAM production. HBM in development — CXMT HBM3e samples reportedly shipped; projecting ~2M HBM stacks in 2026. 1b DRAM process — SK Hynix/Samsung at 1c. | SK Hynix 1c DRAM HBM4; Samsung 1c DRAM HBM4 (4nm base die); Micron HBM4 HVM. Blackwell/Rubin GPU demand running HBM demand far above supply. SK Hynix 2026 HBM supply sold out. | ~2-3 years behind at DRAM process node; HBM gap larger — CXMT HBM stacks not yet at commercial volume while Western HBM4 ships at >$600/stack; HBM gap is the binding Huawei Ascend production constraint | Narrowing slowly — CXMT advancing steadily; HBM capability may reach commercial volume by 2027-2028; but Western HBM4E and HBM5 development will maintain performance gap; China's domestic DRAM is becoming self-sufficient for commodity DRAM (DDR5 for PC/mobile) much faster than for HBM |
| NAND flash | YMTC (Yangtze Memory, Wuhan): 232-layer 3D NAND in production; competitive with Samsung/SK Hynix/Micron on bit density; YMTC is the least-disadvantaged Chinese semiconductor producer relative to its Western counterparts. Facing US entity list restrictions limiting customer access. | Samsung V9 (9th gen NAND); SK Hynix 238-layer; Micron 232-layer QLC. All producing at scale. YMTC technically competitive at cell level but faces distribution restrictions. | Narrowest technology gap in Chinese semiconductor manufacturing — YMTC is within 1 generation of Western leading NAND; Chinese domestic smartphone/PC/datacenter NAND demand can be substantially served domestically | Most advanced bifurcation layer — NAND is effectively bifurcating at the product level already; YMTC serves China domestic market; Western NAND serves non-China; YMTC's entity list status is the primary constraint on global expansion |
| Semiconductor equipment | NAURA: CVD, oxidation, diffusion, cleaning — competitive at 28nm. AMEC: dielectric etch equipment competitive at 28nm; some 7nm-class etch. SMEE: DUV lithography development at 28nm (not yet at ASML ArF-i quality). SciCarrier: immersion DUV lithography development (Huawei-backed). All: zero EUV capability. | ASML: 100% EUV monopoly; DUV NXT series at ~35 WSPH throughput. Applied Materials, Lam Research, KLA: dominant in CVD, etch, ALD, metrology at advanced nodes. Tokyo Electron: critical CVD and coater/developer. | Largest capability gap of any supply chain layer; 10-15 year lag on leading equipment; Chinese domestic equipment adequate for 28nm-90nm; inadequate for sub-7nm even with existing SMIC tools if those tools require Western spare parts and consumables | Slowest-closing gap; equipment development requires tooling, manufacturing precision, and field experience that takes decades to accumulate; NAURA and AMEC making genuine progress at mature nodes; leading-edge equipment gap may narrow to 5-7 years by 2030 but will not close within this decade; China's primary near-term vulnerability is consumables (photoresists, process gases, slurries) that require ongoing Western import |
| EDA / IP / design tools | Empyrean: PCB/IC layout tools competitive at 28nm; limited advanced node support. Xpeedic: RF simulation. Several IP core providers for mature nodes (ARM licensees, MIPS clones). No domestic EDA tools at TSMC N3/N2 capability level. | Synopsys, Cadence, Mentor (Siemens): effectively monopolistic at leading-edge EDA. All three have export control restrictions for advanced node EDA to China. ARM: dominant CPU/GPU IP — Huawei continuing ARM licensing under existing agreement. | Second-largest gap after equipment; leading-edge EDA (process design kits for N3/N2, DRC, LVS at advanced nodes) requires intimate knowledge of foundry process parameters that Chinese EDA companies cannot access; designing at SMIC N+2 is possible with existing tools; designing at TSMC N2 class requires tool access Chinese companies do not have | Widening at leading edge — SMIC's process advancement ceiling is partially determined by EDA tool capability; domestic EDA improving at mature nodes but trailing at leading edge; ARM's decision whether to renew Huawei's architecture license when it expires is a critical 2025-2026 inflection point |
| AI compute (accelerator + software) | Huawei Ascend 950PR (1.56 PFLOPS FP4, SMIC 7nm, 750K units 2026); CloudMatrix 384 system (competitive at rack level, 4.1x NVL72 power penalty); CANN/MindSpore/Pangu going open-source; ByteDance $5.6B Ascend 950PR commitment; Beijing mandate: stop buying NVIDIA, use Ascend. Chinese AI chip makers captured ~41% of Chinese AI accelerator server market in 2025. | NVIDIA Vera Rubin (TSMC N3, 50 PFLOPS FP4); AMD MI455X (TSMC N2, 432GB HBM4); Google TPU v6; Broadcom custom ASIC. CUDA ecosystem (20 years, millions of developers) is the structural advantage no hardware spec can bridge. | ~13x single-chip performance gap (950PR at 1.56 PFLOPS vs Vera Rubin at 20 PFLOPS FP4); but gap is partially closed at system level (CloudMatrix 384 vs NVL72); the more durable gap is software ecosystem depth — CANN vs CUDA represents a 15-20 year development difference | Most complete bifurcation — H20 ban April 2025 eliminated last legal NVIDIA product for China; Beijing September 2025 GPU directive mandated Ascend adoption; two fully separate AI compute ecosystems now exist; the bifurcation at this layer is permanent under current policy and would require a fundamental US-China technology policy reversal to reverse |
The EUV Export Control — The Mechanism Maintaining the Process Gap
The most important single supply chain control in the US-China semiconductor bifurcation is the EUV lithography export restriction. ASML's EUV scanners — the only tools capable of printing sub-7nm features in a single exposure — have been restricted from export to China since 2019 under Dutch export control regulations coordinated with US policy. This restriction is not about a single chip or a single product; it is about the manufacturing tool without which no leading-edge chip can be made at competitive volume and yield. Every TSMC N3/N2 chip, every Samsung SF3/SF2 chip, every Intel 18A chip in the world was made possible by ASML EUV scanners. China does not have a single ASML EUV scanner and, under current policy, will not receive one. The entire performance gap between SMIC N+2 and TSMC N2 — approximately five process generations — is maintained primarily by this one export control.
Understanding the EUV control requires understanding what it does and does not prevent. It does not prevent China from manufacturing chips — SMIC has demonstrated 7nm-class production without EUV using aggressive DUV multipatterning, confirming that the control's purpose is not absolute manufacturing prohibition but pace-of-advancement limitation. What EUV controls prevent is China achieving sub-7nm density at the yield rates that make commercial AI accelerator production economically viable. SMIC's DUV multipatterning approach requires more mask layers per wafer (higher cost, lower throughput), achieves lower final density (fewer transistors per mm²), and produces lower yields due to accumulated overlay errors across multiple exposures. The result is that SMIC's 7nm-class chips cost more per die, perform less per die, and are produced less efficiently than TSMC's EUV 5nm chips. EUV export controls do not eliminate China's semiconductor manufacturing capability; they cap its performance ceiling and inflate its production cost — which is sufficient to maintain a commercially significant performance and efficiency gap for as long as the controls hold.
The domestic Chinese response to EUV restriction has two tracks. The first is perfecting DUV multipatterning at SMIC — engineering excellence at maximizing what is achievable without EUV. This has been more successful than most Western analysts predicted: the Kirin 9000S in 2023 proved 7nm-class density is achievable at commercial volume with DUV-only tools. The second track is developing a domestic EUV alternative. SciCarrier (backed by Huawei) and SMEE (Shanghai Micro Electronics Equipment) are working on domestic lithography. SMEE has demonstrated 28nm capable tools. Domestic EUV is qualitatively different from SMEE's 28nm tool — it requires a plasma extreme ultraviolet light source, tin droplet targeting lasers, multilayer optics, and precision mechanics all developed from first principles, representing arguably the most technically demanding manufacturing engineering project in China's history. Independent assessments place genuine domestic EUV capability — not demonstrated, but commercial-volume capable — at 5-10 years away under sustained investment. China's semiconductor self-sufficiency at leading-edge is primarily a lithography problem.
China's Counter-Leverage — Gallium, Germanium, and Critical Materials
The bifurcation is not a one-sided story of Western export controls constraining Chinese semiconductor capability. China has deployed its own supply chain leverage through export restrictions on materials where it holds dominant global production positions. Gallium and germanium — both critical for compound semiconductor manufacturing — are produced globally in significant volumes only in China. Gallium is a byproduct of aluminum smelting and is used in GaN semiconductors, III-V compound semiconductors for defense RF, solar cells, and LEDs. China produces approximately 80% of the world's gallium. Germanium is used in fiber optic cables, infrared optics, and as a substrate for specialized high-efficiency solar cells and some semiconductor processes. China produces approximately 60% of global germanium.
In July 2023, China imposed export restrictions on gallium and germanium, requiring export licenses for compounds and metals of both elements. In December 2024, China expanded restrictions to include antimony (used in flame retardants and some semiconductor processes) and in 2025 extended to graphite (critical for EV battery anodes and some semiconductor processes). These restrictions are calibrated for signaling as much as for commercial effect — gallium and germanium can be produced outside China but at substantially higher cost and with significant lead time to develop new supply. Defense and aerospace programs that depend on GaN-on-SiC or GaAs semiconductors are most acutely exposed because they cannot easily substitute materials or qualify alternate supply chains quickly. The restrictions establish that the bifurcation imposes costs on both sides and that China has a degree of reciprocal supply chain leverage over the Western ecosystem even as the Western ecosystem maintains a larger technology capability advantage over China's domestic supply chain.
The 28nm Frontier — The Next Policy Battleground
The most actively debated supply chain policy question in the US-China semiconductor context as of 2026 is whether to extend export controls to the 28nm node. The current control architecture focuses on sub-14nm processes and the equipment (primarily EUV) and software (advanced node EDA) necessary to produce them. SMIC is aggressively expanding 28nm capacity at Shanghai, Shenzhen, and Beijing, and is doing so with equipment already purchased from Western suppliers before controls tightened. The concern in Washington is that a large, low-cost Chinese 28nm manufacturing base serves the global market for mature node chips — MCUs, analog ICs, RF front-ends, power management — that are critical to automotive, industrial, and consumer electronics supply chains globally. Chinese 28nm chips at SMIC prices could displace Western mature node producers (GlobalFoundries, TSMC's mature nodes, United Microelectronics) commercially.
The policy argument against extending controls to 28nm is that it would be extremely difficult to enforce (28nm equipment is widely deployed globally and cannot be meaningfully restricted without alienating allies who themselves produce 28nm) and that the commercial disruption of global supply chains for mature node chips — where China is already a major supplier — would impose significant costs on US and allied industries without a proportionate security benefit. The policy argument for extension is that allowing China to dominate the 28nm commodity layer of the semiconductor supply chain creates economic leverage and supply chain dependency that is strategically problematic even if mature node chips do not directly enable military capability. The 28nm frontier debate will shape the next phase of the bifurcation more than any development in advanced node technology — because it determines whether the bifurcation remains a capability-tier phenomenon (advanced nodes separate, mature nodes integrated) or becomes a comprehensive stack-level decoupling.
Bifurcation Scorecard — What China Has Achieved and What Remains Constrained
| Dimension | China achieved | Still constrained |
|---|---|---|
| Manufacturing (foundry) | 7nm-class chips in commercial volume without EUV (Kirin 9000S proof-of-concept 2023); 28nm-90nm self-sufficient; SMIC 50K WSPM advanced node capacity end 2025 | Sub-7nm density impossible with current tools; DUV multipatterning ceiling hard at ~7nm effective density; EUV export control holds |
| Memory (DRAM) | CXMT DDR5 in production, ~15% of global DRAM production capacity by 2026; Chinese domestic PC/mobile DRAM demand increasingly served domestically; 1b DRAM capability | HBM not yet at commercial volume (CXMT ~2M stacks 2026 vs NVIDIA demand of tens of millions); 1b vs 1c DRAM generation behind; HBM4 base die requires advanced foundry process China does not have |
| Memory (NAND) | YMTC 232-layer NAND technically competitive with Western leaders; serving Chinese domestic smartphone and SSD market; demonstrably world-class 3D NAND engineering | Entity list limits global customer access; YMTC cannot sell to Apple, Google, Microsoft, or Samsung devices; confined to domestic market and limited non-Western customers |
| AI compute | Huawei Ascend 950PR at 1.56 PFLOPS FP4; CloudMatrix 384 system-level competitiveness for inference; ByteDance $5.6B domestic commitment; Chinese AI labs demonstrating algorithmic efficiency compensating for hardware gap (DeepSeek R1) | ~13x single-chip compute gap vs NVIDIA Vera Rubin; HBM dependency unsolved for Ascend production scale; CANN vs CUDA 15-20 year ecosystem gap; training at frontier scale still requires more hardware than HBM-constrained Ascend production can deliver |
| Equipment | NAURA and AMEC competitive at 28nm for CVD, etch; SMEE 28nm DUV development; domestic equipment import substitution accelerating at mature nodes; NAURA PE tool improvements measurable year over year | Zero domestic EUV; zero domestic High-NA EUV; leading-edge lithography, metrology, and ALD at sub-7nm still entirely Western; Western spare parts and consumables still entering China through unmonitored channels but this may tighten |
| Critical materials leverage | Gallium export controls (July 2023) covering ~80% of global production; germanium controls covering ~60% of production; antimony and graphite restrictions added 2024-2025; demonstrates reciprocal supply chain leverage even as overall technology gap remains | Gallium and germanium price increases have not yet translated into production disruption for Western semiconductor makers — substitutes and stockpiles have buffered; full commercial impact depends on controls tightening further and stockpiles depleting |
Key Questions — China Semiconductor Bifurcation
Is the bifurcation reversible? At the AI compute layer, almost certainly not under current political conditions — H20 ban has eliminated all legal NVIDIA products for Chinese buyers, Beijing's GPU directive has mandated Ascend adoption, and two years of infrastructure investment on both sides have created ecosystem commitments that would take years to unwind even if policy reversed completely. At the foundry layer, reversal would require ASML to begin exporting EUV to China — politically inconceivable in the current US-Dutch-Japan technology coalition context. At the mature node and memory layers, the bifurcation is less complete and more reversible in principle, but the commercial investment in domestic alternatives makes reversal economically irrational for Chinese companies even if policy permitted it. The operational conclusion is that the bifurcation should be treated as structurally permanent at the advanced node and AI compute layers for strategic planning purposes.
Does China's algorithmic innovation compensate for hardware capability gaps? Partially and increasingly. DeepSeek R1's demonstration that frontier-class AI model results are achievable with dramatically less compute than US labs assumed was necessary — using techniques like mixture of experts, distillation, and speculative decoding that reduce compute requirements — represents a genuine algorithmic response to hardware constraints. If Chinese AI researchers systematically develop algorithmic approaches that require less compute for equivalent results, the hardware performance gap matters less than raw FLOPS comparisons suggest. However, there are absolute limits: training at the frontier (models larger than current state-of-the-art) requires raw compute scale that algorithmic efficiency can only partially offset. China's ability to maintain frontier AI development is bounded by both HBM supply (which constrains how many Ascend chips can be packaged) and by inference serving at scale (which requires the cluster architecture that Huawei is building but at a significant power efficiency disadvantage).
What is the most underappreciated supply chain risk in the bifurcation? The Western tool and consumable dependency of SMIC and CXMT. Both companies expanded aggressively by acquiring Western equipment before controls tightened, and both are running fabs full of Applied Materials CVD chambers, Lam Research etch tools, KLA metrology systems, and Tokyo Electron coaters that require ongoing supply of Western-sourced consumables (photoresists from JSR, Tokyo Ohka, and Sumitomo; process gases; chemical mechanical planarization slurries). These consumables cannot be substituted with domestic alternatives in the near term without significant yield degradation. China's domestic semiconductor manufacturing capability is not nearly as independent as the existence of SMIC N+2 production suggests — it is dependent on ongoing imports of specialty chemicals and spare parts that, if effectively controlled, would constrain SMIC's ability to maintain yield at current levels. The enforcement of consumables controls is the underreported supply chain risk that could matter more than any new equipment restriction in the near term.
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